1. Field of the Invention
The invention relates to a transmission system comprising a control circuit which circuit includes a comparator for comparing a first input signal and a second input signal.
2. Description of the Related Art
Such a transmission system may be used, for example, for transmitting signals of the Synchronous Digital Hierarchy (SDH). For example, a multiplexer then combines various plesiochronous or also synchronous signals (for example STM-1 signal) to an STM16 signal (STM=Synchronous Transport Module). A synchronization circuit in the multiplexer then effects a clock alignment of an incoming signal and an outgoing signal. The justification actions necessary for the clock alignment are then carried out with pointer bytes. Such justification actions are also denoted as pointer actions in the Synchronous Digital Hierarchy.
In a demultiplexer of the transmission system, the plesiochronous or synchronous signals are then recovered by means of desynchronization circuits. Because of the frame structure and the pointer actions, phase errors occur between the input signal and the output signal of the transmission system.
Said transmission system is known from EP 0 507 385 A2 or from the article "Network synchronization--A Challenge for SDH/SONET?" by M. J. Klein and R. Urbansky, IEEE Communications Magazine, Sep. 1993, vol. 31, no. 9, pages 42 to 50. A synchronized signal (STM-1) signal of the Synchronous Digital Hierarchy is then adapted to a read clock signal. The read clock signal is generated by the first phase-locked loop (PLL) which includes at least a first comparator (phase detector), a controller and a controllable oscillator. The first comparator is supplied with the oscillator signal (read clock signal) and, for example, a control signal by a network management system of the transmission system.
For adapting the synchronized signal to the read clock signal, justification values are processed in pointers (pointer action). For the clock adaptation is used a buffer store which is controlled by a write and a read counter. The write counter is controlled by a data analyzer (pointer interpreter), which determines from the pointer values the justification values contained in the incoming synchronized signal. The read counter forms part of a control circuit which includes a subtracter, a low-pass filter, a justification decision circuit and a data generator (pointer generator). The low-pass filter is used for reducing the high-frequency phase error caused by pointer actions in the incoming signal and for reducing the frame structure-caused phase error between the input signal and output signal of the transmission system. In the justification decision circuit there is an integrator available which shifts the jitter spectrum to the high-frequency range (jitter is high-frequency phase error). A low-frequency phase error cannot be eliminated by said measures.
The justification decision circuit forms a positive justification value if the value produced by the integrator exceeds a positive threshold. If the value produced by the integrator falls short of a negative threshold, the justification decision circuit produces a negative justification value. The pointer generator generates pointer values for the outgoing signal and controls the read counter as a function of the justification values and the STM-1 frame. The read counter is stopped in the case of a positive justification decision. In the case of a negative justification decision, the read counter is enabled one data byte earlier for counting during a frame.